Work = VLSI design. Have been crazy about computers ever since the knowledge of their existence... wanted to know how 'exactly' do they work. Which led me to ASU, pursuing masters in electrical engineering. For details see my resume (pdf).
Advanced VLSI Design last Spring semester has been the most productive course at ASU. Two worthwhile projects:
- 8KB SRAM bank design in TSMC .25u process. The design incorporated the 11:128 Decoder, 6T SRAM cell and Sense Amplifier Read running at 300 Mhz under all process variations. Maximum functional speed was 350 Mhz at nominal corner. Detailed design report will be up soon.
- 32-entry Translation Lookaside Buffer supporting variable page sizes from 4kB to 16MB. Register file based CAM (Content Addressable Memory) cell with a NAND matchline was used. Same TSMC .25u process used. The project is currently underway and we hope to achieve a functional speed of at least 333 Mhz where in CAM operation and READ operation are executed in a single clock period. Detailed design report will be up soon.
Currently employed as a Research Assistant under Dr.Kevin Cao in the Electrical Engineering Department at Arizona State University. I am currently working on modeling, characterization and circuit design for carbon nanotube transistors : research is still in its nascent stage and slow since large scale fabrication is not feasible at present. It could be one of the potential succesors to CMOS if the process challenges are met soon.
Presented our work (Compact Modeling of Carbon Nanotubes, model developed by Asha Balijepalli) at ISLPED 2007 and won the Best Paper award. For more details about the model and ongoing research work, see ASU's PTM website. I intend to explore a CNT-FET (Carbon Nanotube Field Effect Transistor)'s potential for analog design.
Publications:
- A. Balijepalli, S. Sinha, Y. Cao, "Compact modeling of carbon nanotube transistor for early stage process-design exploration," ISLPED, 2007 (Best Paper Award).